Heat treatment apparatus emitting flash of light

ABSTRACT

Flash lamps connected to short-pulse circuits and flash lamps connected to long-pulse circuits are alternately arranged in a line. The duration of light emission from the flash lamps connected to the long-pulse circuits is longer than the duration of light emission from the flash lamps connected to the short-pulse circuits. A superimposing of a flash of light with a high peak intensity from the flash lamps that emit light for a short time and a flash of light with a gentle peak from the flash lamps that emit light for a long time can increase the temperature of even a deep portion of a substrate to an activation temperature or more without heating a shallow portion near the substrate surface more than necessary. This achieves the activation of deep junctions without causing substrate warpage or cracking.

CROSS REFERENCE TO RELATED APPLICATION

This application is a continuation of U.S. application Ser. No.14/176,262, filed Feb. 10, 2014, which is a continuation of U.S.application Ser. No. 13/298,892, filed Nov. 17, 2011 (now U.S. Pat. No.8,686,320, issued Apr. 1, 2014), which is a continuation of U.S.application Ser. No. 11/970,002, filed Jan. 7, 2008 (now U.S. Pat. No.8,173,937, issued May. 9, 2012), which claims the benefit of JapaneseApplication Serial No. JP2007-029926 filed Feb. 9, 2007, the contents ofwhich are incorporated by this reference.

BACKGROUND OF THE INVENTION

Field of the Invention

The present invention relates to a heat treatment apparatus thatirradiates a substrate, such as a semiconductor wafer and a glasssubstrate for a liquid crystal display device, with a flash of light,thereby heating the substrate.

Description of the Background Art

Conventionally, lamp annealers employing halogen lamps have beentypically used in the step of activating ions in a semiconductor waferafter ion implantation. Such lamp annealers carry out the activation ofions in a semiconductor wafer by heating (or annealing) thesemiconductor wafer to a temperature of, for example, about 1000° C. toabout 1100° C. Such heat treatment apparatuses utilize the energy oflight emitted from the halogen lamps to raise the temperature of asubstrate at a rate of about hundreds of degrees per second.

In recent years, with the increasing degree of integration ofsemiconductor devices, it has been desired to provide a shallowerjunction as the gate length decreases. It has turned out, however, thateven the execution of the process of activating ions in a semiconductorwafer by using the aforementioned lamp annealers which raise thetemperature of a semiconductor wafer at a rate of about hundreds ofdegrees per second produces a phenomenon in which the ions such as boronand phosphorus implanted in the semiconductor wafer are deeply diffusedby heat. The occurrence of such a phenomenon causes the depth of thejunction to exceed a required level, which can be a hindrance to gooddevice formation.

In view of this, techniques for irradiating the surface of asemiconductor wafer with a flash of light by using xenon flash lamps(hereinafter also referred to simply as “flash lamps”) to raise thetemperature of only the surface of the ion-implanted semiconductor waferin an extremely short time (several milliseconds or less) are proposedfor example in U.S. Pat. Nos. 6,998,580 and 6,936,797. The flash lampshave a spectral distribution of radiation ranging from ultraviolet tonear-infrared regions. The wavelength of light emitted from the flashlamps is shorter than that emitted from conventional halogen lamps, andit approximately coincides with a basic absorption band of a siliconsemiconductor wafer. It is therefore possible to, when a semiconductorwafer is irradiated with a flash of light emitted from the flash lamps,rapidly raise the temperature of the semiconductor wafer with a smallamount of light transmitted through the semiconductor wafer. It has alsoturned out that a flash of light emitted in an extremely short time ofseveral milliseconds or less can achieve a selective temperature rise ofonly near the surface of the semiconductor wafer. Therefore, anextremely short-time temperature rise using the xenon flash lamps allowsthe execution of only ion activation with no deep ion diffusion.

As described above, the heat treatment apparatuses employing xenon flashlamps are annealers that are essentially suitable for heat treatment ofshallow junctions, the need to, using xenon flash lamps, carry out ionactivation of somewhat deeper junctions than ever has arisen in recentyears. For activation of deeper junctions than ever, conceivable is atechnique of increasing the duration of light emission from flash lampsmore than ever, thereby to raise the temperature of not only the surface(a shallow portion) but also a deep portion of a semiconductor wafer byheat conduction. As a result, the ion activation of a deep portion of asemiconductor wafer below the surface, i.e., the activation of a deepjunction, becomes possible.

However, increasing the duration of light emission from xenon flashlamps so as to raise the temperature of a deep portion increases thesurface temperature of the semiconductor wafer more than necessary, thusundesirably resulting in the occurrence of wafer warpage due to theaction of great thermal stress on the surface, or at worst, theoccurrence of wafer cracking due to an abrupt thermal expansion.

SUMMARY OF THE INVENTION

The invention is intended for a heat treatment apparatus that irradiatesa substrate with a flash of light to heat the substrate.

According to the invention, the heat treatment apparatus includes: aholder holding a substrate; a plurality of flash lamps emitting a flashof light toward the substrate held by the holder; a first lamp drivecircuit causing the flash lamps to emit light for a duration of a firstlight-emission time; and a second lamp drive circuit causing the flashlamps to emit light for a duration of a second light-emission timelonger than the first light-emission time. The first lamp drive circuitis connected to a first lamp group consisting of part of the pluralityof flash lamps, and the second lamp drive circuit is connected to asecond lamp group consisting of the remainder of the plurality of flashlamps.

Since irradiation is given with a mixture of a flash of light with asmall pulse width and a flash of light with a great pulse width, theactivation of a deep junction is possible without causing substratewarpage or cracking.

Preferably, the first lamp group and the second lamp group are soarranged that a flash of light emitted from the first lamp group and aflash of light emitted from the second lamp group are superimposed onone another on a surface of the substrate held by the holder.

This can raise the temperature of even a deep portion of the substrateto an activation temperature or more without heating a shallow portionnear the substrate surface more than necessary, thus achieving theactivation of a deep junction without causing substrate warpage orcracking.

According to one aspect of the invention, the heat treatment apparatusfurther includes a light-emission controller controlling the first lampdrive circuit and the second lamp drive circuit so as to stagger starttiming of light emission from the flash lamps forming the first lampgroup and start timing of light emission from the flash lamps formingthe second lamp group.

This produces wide variations of heat treatment patterns.

It is therefore an object of the invention to provide a heat treatmentapparatus capable of activating a deep junction without causingsubstrate warpage or cracking.

These and other objects, features, aspects and advantages of theinvention will become more apparent from the following detaileddescription of the invention when taken in conjunction with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a side sectional view showing the construction of a heattreatment apparatus according to the invention;

FIG. 2 is a sectional view showing a gas passage in the heat treatmentapparatus of FIG. 1;

FIG. 3 is a cross-sectional view showing the structure of a holder;

FIG. 4 is a plan view of a hot plate;

FIG. 5 is a side sectional view showing the construction of the heattreatment apparatus of FIG. 1;

FIG. 6 is a diagram showing a drive circuit for a xenon flash lamp;

FIG. 7 illustrates an arrangement of a plurality of flash lamps in afirst preferred embodiment;

FIG. 8 is a block diagram showing the structure of a controller;

FIG. 9 shows the transition of the light intensity in the surface of asemiconductor wafer;

FIG. 10 shows the transition of the surface temperature of asemiconductor wafer since the start of light emission;

FIG. 11 is a diagram showing an arrangement of a plurality of flashlamps in a second preferred embodiment;

FIG. 12 is a diagram showing an arrangement of a plurality of flashlamps in a third preferred embodiment;

FIG. 13 shows one example of the transition of the light intensity inthe case where flash lamps with different pulse widths start lightemission with different timing; and

FIG. 14 shows another example of the transition of the light intensityin the case where flash lamps with different pulse widths start lightemission with different timing.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Preferred embodiments of the invention are now described in detail withreference to the drawings.

<1. First Preferred Embodiment>

First, the overall construction of a heat treatment apparatus accordingto the invention is summarized. FIG. 1 is a side sectional view showingthe construction of a heat treatment apparatus 1 according to theinvention. The heat treatment apparatus 1 is a flash lamp annealer thatirradiates a generally circular semiconductor wafer W serving as asubstrate with a flash of light to heat the semiconductor wafer W.

The heat treatment apparatus 1 includes a chamber 6 of a generallycylindrical configuration for receiving a semiconductor wafer W therein,and a lamp house 5 including a plurality of flash lamps FL incorporatedtherein. The heat treatment apparatus 1 further includes a controller 3for controlling operating mechanisms provided in the chamber 6 and inthe lamp house 5 to cause the operating mechanisms to perform heattreatment of the semiconductor wafer W.

The chamber 6 is provided under the lamp house 5. The chamber 6 includesa chamber side portion 63 having an inner wall of a generallycylindrical configuration, and a chamber bottom portion 62 covering thelower part of the chamber side portion 63. A space surrounded by thechamber side portion 63 and the chamber bottom portion 62 is defined asa heat treatment space 65. A top opening 60 is formed over the heattreatment space 65. The top opening 60 has a chamber window 61 mountedtherein to produce a blockage.

The chamber window 61 constituting a ceiling portion of the chamber 6 isa disk-shaped member made of quartz, and transmits a flash of lightemitted from the lamp house 5 into the heat treatment space 65. Thechamber bottom portion 62 and the chamber side portion 63 whichconstitute the main body of the chamber 6 are made of, for example, ametal material, such as stainless steel, having high strength and highheat resistance. A ring 631 in the upper part of the inner side surfaceof the chamber side portion 63 is made of an aluminum (Al) alloy or thelike having greater durability against degradation due to exposure tolight than stainless steel.

The chamber window 61 and the chamber side portion 63 are sealed with anO-ring so as to maintain the hermeticity of the heat treatment space 65.Specifically, the O-ring is fitted in between a lower peripheral portionof the chamber window 61 and the chamber side portion 63, and a clampring 90 is caused to abut against an upper peripheral portion of thechamber window 61 and secured to the chamber side portion 63 by screws,thereby forcing the chamber window 61 against the O-ring.

The chamber bottom portion 62 is provided with a plurality of (in thispreferred embodiment, three) upright support pins 70 extending through aholder 7 in order to support the lower surface (a surface opposite fromthe surface exposed to light from the lamp house 5) of the semiconductorwafer W. The support pins 70 are made of, for example, quartz, and areeasy to replace because they are fixed externally of the chamber 6.

The chamber side portion 63 includes a transport opening 66 fortransport of the semiconductor wafer W into and out of the chamber 6.The transport opening 66 is openable and closable by a gate valve 185that pivots about an axis 662. On the opposite side of the chamber sideportion 63 from the transport opening 66, an inlet passage 81 is formed,which introduces a processing gas (for example, an inert gas such asnitrogen (N₂) gas, helium (He) gas, and argon (Ar) gas, or oxygen (O₂)gas, or the like) into the heat treatment space 65. The inlet passage 81has its one end connected through a valve 82 to a gas supply mechanismnot shown, and the other end connected to a gas inlet buffer 83 formedinside the chamber side portion 63. The transport opening 66 is providedwith an outlet passage 86 for exhausting gas inside the heat treatmentspace 65. The outlet passage 86 is connected through a valve 87 to anexhaust mechanism not shown.

FIG. 2 is a sectional view of the chamber 6 taken along a horizontalplane at the level of the gas inlet buffer 83. As shown in FIG. 2, thegas inlet buffer 83 extends over approximately one-third of the innerperiphery of the chamber side portion 63 on the opposite side from thetransport opening 66 shown in FIG. 1. Processing gas introduced throughthe inlet passage 81 to the gas inlet buffer 83 is fed through aplurality of gas supply holes 84 into the heat treatment space 65.

The heat treatment apparatus 1 further includes the holder 7 of agenerally disk-shaped configuration for holding a semiconductor wafer Win a horizontal position within the chamber 6 and preheating the holdingsemiconductor wafer W prior to exposure of a flash of light, and aholder elevating mechanism 4 for moving the holder 7 upwardly anddownwardly relative to the chamber bottom portion 62 serving as thebottom surface of the chamber 6. The holder elevating mechanism 4 shownin FIG. 1 includes a shaft 41 of a generally cylindrical configuration,a movable plate 42, guide members 43 (in this preferred embodiment,three guide members 43 provided around the shaft 41), a fixed plate 44,a ball screw 45, a nut 46, and a motor 40. The chamber bottom portion 62serving as the bottom of the chamber 6 is provided with a bottom opening64 of a generally circular configuration having a diameter smaller thanthat of the holder 7. The shaft 41 made of stainless steel is insertedthrough the bottom opening 64 and connected to the lower surface of theholder 7 (strictly speaking, a hot plate 71 of the holder 7) to supportthe holder 7.

The nut 46 for threaded engagement with the ball screw 45 is fixed tothe movable plate 42. The movable plate 42 is slidably guided by theguide members 43 fixed to and extending downwardly from the chamberbottom portion 62, so as to be vertically movable. The movable plate 42is coupled through the shaft 41 to the holder 7.

The motor 40 is installed on the fixed plate 44 mounted to the lower endportions of the guide members 43, and is connected to the ball screw 45through a timing belt 401. When the holder elevating mechanism 4 movesthe holder 7 upwardly and downwardly, the motor 40 serving as a driverrotates the ball screw 45 under the control of the controller 3 so thatthe movable plate 42 fixed to the nut 46 moves vertically along theguide members 43. As a result, the shaft 41 fixed to the movable plate42 moves vertically, whereby the holder 7 connected to the shaft 41smoothly moves upwardly and downwardly between a position for transferof the semiconductor wafer W (hereinafter referred to as a “transferposition”) shown in FIG. 1 and a position for treatment of thesemiconductor wafer W (hereinafter referred to as a “treatmentposition”) shown in FIG. 5.

A mechanical stopper 451 of a generally semi-cylindrical configuration(a configuration obtained by cutting a cylinder in half in alongitudinal direction) is provided upright and extending along the ballscrew 45 on the upper surface of the movable plate 42. Even if themovable plate 42 moves upwardly beyond a certain upper limit due to anyanomaly, the upper end of the mechanical stopper 451 strikes an endplate 452 provided at the end of the ball screw 45, which therebyprevents an abnormal upward movement of the movable plate 42. Thisavoids an upward movement of the holder 7 above a certain position underthe chamber window 61, thereby preventing a collision between the holder7 and the chamber window 61.

The holder elevating mechanism 4 further includes a manual elevator 49for manually moving the holder 7 upwardly and downwardly duringmaintenance of the interior of the chamber 6. The manual elevator 49includes a handle 491 and a rotary shaft 492. Rotating the rotary shaft492 by means of the handle 491 causes the rotation of the ball screw 45connected through a timing belt 495 to the rotary shaft 492, therebymoving the holder 7 upwardly and downwardly.

An expandable/contractible bellows 47 that surrounds the shaft 41 andextends downwardly from the chamber bottom portion 62 is provided underthe chamber bottom portion 62, with its upper end connected to the lowersurface of the chamber bottom portion 62. The lower end of the bellows47 is mounted to a bellows-lower-end plate 471. The bellows-lower-endplate 471 is mounted to the shaft 41 with screws by a collar member 411.The bellows 47 contracts when the holder elevating mechanism 4 moves theholder 7 upwardly relative to the chamber bottom portion 62, while itexpands when the holder elevating mechanism 4 moves the holder 7downwardly. The expansion and contraction of the bellows 47 maintainsthe hermeticity of the interior of the heat treatment space 65 evenduring the upward and downward movements of the holder 7.

FIG. 3 is a sectional view showing the structure of the holder 7. Theholder 7 includes the hot plate (or heating plate) 71 for preheating (orassist-heating) the semiconductor wafer W, and a susceptor 72 installedon the upper surface of the hot plate 71 (the surface on the side wherethe holder 7 holds the semiconductor wafer W). The shaft 41 that movesthe holder 7 upwardly and downwardly as mentioned above is connected tothe lower surface of the holder 7. The susceptor 72 is made of quartz(or it may be made of aluminum nitride (AlN) or the like) and has on theupper surface pins 75 for preventing misalignment of the semiconductorwafer W. The susceptor 72 is installed on the hot plate 71, with itslower surface in face-to-face contact with the upper surface of the hotplate 71. Thus, the susceptor 72 diffuses and transmits heat energy fromthe hot plate 71 into the semiconductor wafer W placed on the uppersurface of the susceptor 72, and during maintenance, it is removablefrom the hot plate 71 for cleaning.

The hot plate 71 includes an upper plate 73 and a lower plate 74 bothmade of stainless steel. In a space between the upper plate 73 and thelower plate 74, resistance heating wires 76 such as nichrome wires forheating the hot plate 71 are provided, and the space is filled andsealed with an electrically conductive brazing metal containing nickel(Ni). The upper plate 73 and the lower plate 74 have their ends brazedor soldered.

FIG. 4 is a plan view of the hot plate 71. As shown in FIG. 4, the hotplate 71 has a disk-shaped zone 711 and a ring-shaped zone 712concentrically arranged in a central part of the area facing the heldsemiconductor wafer W, and four zones 713 to 716 which are equally andcircumferentially divided portions of a generally ring-shaped areasurrounding the zone 712. There is a slight gap between each of thezones. The hot plate 71 is further provided with three through holes 77receiving the support pins 70 therethrough and circumferentially spaced120° apart from each other in a gap between the zones 711 and 712.

In each of the six zones 711 to 716, the resistance heating wires 76independent of each other are placed so as to make a circuit, therebyforming an individual heater. The heaters incorporated in the zonesindividually heats the zones. The semiconductor wafer W held by theholder 7 is heated by the heaters incorporated in the six zones 711 to716. In each of the zones 711 to 716, a sensor 710 is also provided tomeasure the temperature of each zone using a thermocouple. The sensors710 are connected to the controller 3 through the interior of thegenerally cylindrical shaft 41.

In heating the hot plate 71, the controller 3 controls the amount ofpower supply to the resistance heating wires 76 in each zone so that thetemperatures of the six zones 711 to 716 measured by the sensors 710reach a certain preset temperature. The temperature control in each zoneby the controller 3 is done by PID (Proportional, Integral, Derivative)control. In the hot plate 71, the temperatures of the zones 711 to 716are continually measured until the completion of the heat treatment ofthe semiconductor wafer W (or the completion of the heat treatment ofall semiconductor wafers W when there are a plurality of semiconductorwafers W to be successively heat treated), and the amount of powersupply to the resistance heating wires 76 in each zone is individuallycontrolled, that is, the temperature of the heater in each zone isindividually controlled, so that the temperature of each zone ismaintained at a preset temperature. The preset temperature of each zonecan be changed by an individually determined offset value from areference temperature.

The resistance heating wires 76 in each of the six zones 711 to 716 areconnected through power lines passing through the interior of the shaft41 to a power source (not shown). The power lines extending from thepower source to each zones are disposed inside a stainless tube filledwith an insulator of magnesia (magnesium oxide) or the like so as to beelectrically insulated from each other. The interior of the shaft 41 isopen to the atmosphere.

Next, the lamp house 5 includes a light source including a plurality of(in this preferred embodiment, 30) xenon flash lamps (hereinafterreferred to simply as “flash lamps”) FL, and a reflector 52 provided tocover over the light source. A lamp light irradiation window 53 ismounted in a bottom portion of an enclosure 51 of the lamp house 5. Thelamp light irradiation window 53 constituting a floor portion of thelamp house 5 is a plate-like member made of quartz. The provision of thelamp house 5 over the chamber 6 places the lamp light irradiation window53 in opposed relation to the chamber window 61. The lamp house 5 heatsthe semiconductor wafer W by irradiating the semiconductor wafer W heldby the holder 7 within the chamber 6 with a flash of light from theflash lamps FL through the lamp light irradiation window 53 and thechamber window 61.

The plurality of flash lamps FL are rod-like lamps having an elongatedcylindrical configuration. In the first preferred embodiment, the flashlamps FL are arranged in an array in a plane so that their respectivelongitudinal directions are in parallel with each other along a majorsurface of the semiconductor wafer W held by the holder 7 (i.e., along ahorizontal direction). Accordingly, the plane defined by the array ofthe flash lamps FL is a horizontal plane.

FIG. 6 is a diagram showing a drive circuit for xenon flash lamp FL. Thexenon flash lamps FL each include a rod-like glass tube (or dischargetube) 92 containing xenon gas sealed therein and having at opposite endspositive and negative electrodes connected to a capacitor 93, and atrigger electrode 91 affixed to the outer peripheral surface of theglass tube 92. The capacitor 93 receives a given voltage applied from apower supply unit 95 and accumulates charge induced by the appliedvoltage. A circuit for connecting the capacitor 93 and the electrodes ofthe glass tube 92 is provided with a coil 94.

Since xenon gas is electrically insulative, no current flows in theglass tube 92 in a normal state even in the presence of accumulatedcharge on the capacitor 93. However, if a trigger switch SW is turned onand a high voltage is applied to the trigger electrode 91, to cause anelectrical breakdown, accumulated electricity on the capacitor 93 flowsmomentarily in the glass tube 92, and the resultant Joule heat heats thexenon gas to cause light emission. That is, the start timing of lightemission from the xenon flash lamps FL is determined by the timing ofswitching of the trigger switch SW from OFF to ON. Such xenon flashlamps FL have the property of being capable of emitting much moreintense light than a light source that stays lit continuously becauseelectrostatic energy previously accumulated on the capacitor 93 isconverted into an ultrashort light pulse ranging from 0.1 millisecond to10 milliseconds. The trigger switch SW may, for example, be anelectrical switching element such as a thyristor.

Now, in the first preferred embodiment, 30 flash lamps FL are provided,each accompanied by one drive circuit as shown in FIG. 6. The durationof light emission from the xenon flash lamps FL is determined by thecapacitance of the capacitor 93 and the inductance of the coil 94. It isknown that the pulse period of a flash of light emitted from the flashlamps FL, i.e., the duration of light emission from the flash lamps FLfor each irradiation of a flash of light, is proportional to half of thesquare of the product of the capacitance of the capacitor 93 and theinductance of the coil 94. Thus, the duration of light emission from theflash lamp FL becomes longer as the capacitance of the capacitor 93 orthe inductance of the coil 94 increases.

The first preferred embodiment employs two types of lamp drive circuitseach having a different inductance of the coil 94. The thirty flashlamps FL each are connected to either of the two types of drivecircuits. FIG. 7 shows the arrangement of a plurality of flash lamps FLin the first preferred embodiment. As shown in FIG. 7, the thirty flashlamps FL each are connected to either a short-pulse circuit SP or along-pulse circuit LP. The short-pulse circuit SP is a drive circuitincluding the capacitor 93 with capacitance of 750 μF and the coil 94with inductance of 260 μH in the configuration of FIG. 6. The long-pulsecircuit LP is a drive circuit including the capacitor 93 withcapacitance of 750 μF and the coil 94 with inductance of 2200 μH in theconfiguration of FIG. 6. The duration of light emission from flash lampsFL1 connected to the short-pulse circuit SP is approximately 0.1milliseconds, while the duration of light emission from flash lamps FL2(indicated by hatched lines in FIG. 7 for easier understanding)connected to the long-pulse circuit LP is approximately 3.0milliseconds. That is, the long-pulse circuit LP includes the coil 94with larger inductance than the coil 94 in the short-pulse circuit SP,so that the duration of light emission from the flash lamps FL2connected to the long-pulse circuit LP is longer than the duration oflight emission from the flash lamps FL1 connected to the short-pulsecircuit SP.

In the first preferred embodiment, as shown in FIG. 7, the flash lampsFL1 and the flash lamps FL2 are alternately arranged in a line. Morespecifically, the thirty flash lamps FL (generically referred to as“flash lamps FL” when it is not necessary to distinguish between theflash lamps FL1 and the flash lamps FL2) are divided into two lampgroups each consisting of fifteen flash lamps FL. One of the lamp groups(a first lamp group) is connected to the short-pulse circuit SP, and theother of the lamp groups (a second lamp group) is connected to thelong-pulse circuit LP. Then, the flash lamps FL1 forming the first lampgroup and the flash lamps FL2 forming the second lamp group are arrangedalternately. Although in FIG. 7, for convenience in drawing, the fifteenflash lamps FL1 are connected to one short-pulse circuit SP, and thefifteen flash lamps FL2 are connected to one long-pulse circuit LP, itis to be noted that, as described above, one flash lamp FL correspondsto one drive circuit so that each of the short-pulse circuit SP and thelong-pulse circuit LP in FIG. 7 comprehensively represents fifteen drivecircuits.

The reflector 52 is provided to cover over the whole of the plurality offlash lamps FL. The fundamental function of the reflector 52 is toreflect a flash of light emitted from the plurality of flash lamps FLtoward the holder 7. The reflector 52 is a plate made of an aluminum(Al) alloy and has a surface (the surface facing the flash lamps FL)roughened by abrasive blasting to produce a satin finish thereon. Thereason for such roughening is that the reflector 52 having a perfectmirror surface causes a regular pattern in the intensity of reflectedlight from the plurality of flash lamps FL, thereby deteriorating theuniformity of a surface temperature distribution across thesemiconductor wafer W.

The controller 3 controls the aforementioned various operatingmechanisms installed in the heat treatment apparatus 1. FIG. 8 is ablock diagram showing the structure of the controller 3. The controller3 is similar in hardware construction to a typical computer.Specifically, the controller 3 includes a CPU 31 performing variouscomputation processes, a ROM 32 serving as read-only memory for storinga basic program therein, a RAM 33 serving as readable/writable memoryfor storing various pieces of information therein, and a magnetic disk34 for storing control software and data therein, all of which areconnected to a bus line 39.

The bus line 39 is electrically connected to the motor 40 in the holderelevating mechanism 4 for moving the holder 7 upwardly and downwardly inthe chamber 6, and to a trigger control circuit 38. The trigger controlcircuit 38 is connected to the trigger switches SW of the plurality offlash lamps FL and controls the turning on and off of the triggerswitches SW. The CPU 31 in the controller 3, by execution of controlsoftware stored in the magnetic disk 34, controls the motor 40 to adjustthe level of the holder 7, and controls the trigger control circuit 38so that the plurality of flash lamps FL emit light with given timing,i.e., the trigger switches SW are turned on with given timing.

The bus line 39 is further electrically connected to a display unit 21and an input unit 22. The display unit 21 is configured as, for example,a liquid crystal display or the like, and displays various kinds ofinformation such as the result of processing and recipe content. Theinput unit 22 is configured as, for example, a keyboard, a mouse, or thelike, and receives input of commands, parameters, and the like. Anoperator using the apparatus can input commands, parameters, and thelike using the input unit 22 while confirming the contents displayed onthe display unit 21. Alternatively, the display unit 21 and the inputunit 22 may be configured integrally as a touch panel.

In addition to the aforementioned components, the heat treatmentapparatus 1 includes various cooling structures in order to prevent anexcessive temperature rise in the chamber 6 and in the lamp house 5 dueto heat energy generated from the flash lamps FL and the hot plate 71during the heat treatment of the semiconductor wafer W. For example, thechamber side portion 63 and the chamber bottom portion 62 of the chamber6 are provided with a water cooling tube (not shown). The lamp house 5has an air-cooling structure including a gas supply pipe 55 and anexhaust gas pipe 56 for forming a gas flow inside the lamp house 5 toexhaust heat (see FIG. 1). Air is also supplied into a gap between thechamber window 61 and the lamp light irradiation window 53, therebycooling the lamp house 5 and the chamber window 61.

Next, a procedure for the treatment of the semiconductor wafer W in theheat treatment apparatus 1 is briefly described. The semiconductor waferW to be treated herein is a semiconductor substrate doped withimpurities (ions) by an ion implantation process. The activation of theimplanted impurities is achieved by a flash heating process in the heattreatment apparatus 1.

First, the holder 7 is moved downwardly from the treatment positionshown in FIG. 5 to the transfer position shown in FIG. 1. The “treatmentposition” is the position of the holder 7 when the semiconductor wafer Wis exposed to a flash of light emitted from the flash lamps FL, andspecifically, the position of the holder 7 within the chamber 6 shown inFIG. 5. The “transfer position” is the position of the holder 7 when thesemiconductor wafer W is transported into and out of the chamber 6, andspecifically, the position of the holder 7 within the chamber 6 shown inFIG. 1. A reference position of the holder 7 in the heat treatmentapparatus 1 is the treatment position, and prior to the treatment, theholder 7 is in the treatment position. At the start of the treatment,the holder 7 is moved downwardly to the transfer position. As shown inFIG. 1, the holder 7 after moved downwardly to the transfer position isin close proximity to the chamber bottom portion 62, and the upper endsof the support pins 70 protrude through the holder 7 upwardly above theholder 7.

When the holder 7 is moved downwardly to the transfer position, thevalves 82 and 87 are opened to introduce nitrogen gas at roomtemperature into the heat treatment space 65 of the chamber 6.Subsequently, the gate valve 185 is opened to open the transport opening66, and the ion-implanted semiconductor wafer W is transported throughthe transport opening 66 into the chamber 6 and placed onto theplurality of support pins 70 by a transport robot outside the heattreatment apparatus 1.

The amount of nitrogen gas purged into the chamber 6 during thetransport of the semiconductor wafer W shall be about 40 liters perminute. The supplied nitrogen gas flows in the chamber 6 from the gasinlet buffer 83 in the direction indicated by the arrows AR4 of FIG. 2,and is exhausted through the outlet passage 86 and the valve 87 shown inFIG. 1 by a utility exhaust system. Part of the nitrogen gas suppliedinto the chamber 6 is exhausted also from a discharge outlet (not shown)inside the bellows 47. In the following steps described below, nitrogengas is always continuously supplied into and exhausted from the chamber6, and the amount of supply of nitrogen gas is varied in accordance withthe process steps of the semiconductor wafer W.

After the semiconductor wafer W is transported into the chamber 6, thegate valve 185 closes the transport opening 66. Then, the holderelevating mechanism 4 moves the holder 7 upwardly from the transferposition to the treatment position close to the chamber window 61. Inthe course of the upward movement of the holder 7 from the transferposition, the semiconductor wafer W is transferred from the support pins70 to the susceptor 72 of the holder 7 and is placed and held on theupper surface of the susceptor 72. With the upward movement of theholder 7 to the treatment position, the semiconductor wafer W on thesusceptor 72 is also held in the treatment position.

The six zones 711 to 716 of the hot plate 71 have already been heated upto a certain temperature by the heaters (the resistance heating wires76) individually provided within the zones (between the upper plate 73and the lower plate 74). By the holder 7 moving upwardly to thetreatment position to bring the semiconductor wafer W into contact withthe holder 7, the semiconductor wafer W is preheated by the heaters inthe hot plate 71 and gradually increases in temperature.

Preheating the semiconductor wafer W in the treatment position for about60 seconds increases the temperature of the semiconductor wafer W up toa preset preheating temperature T1. The preheating temperature T1 shallbe in the range of approximately 200° C. to approximately 800° C.,preferably approximately 350° C. to approximately 550° C., at whichthere is no apprehension that impurities implanted in the semiconductorwafer W are diffused by heat. A distance between the holder 7 and thechamber window 61 is adjustable to any value by controlling the amountof rotation of the motor 40 of the holder elevating mechanism 4.

After a lapse of the preheating time of about 60 seconds, with theholder 7 remaining in the treatment position, a flash of light isemitted from the flash lamps FL in the lamp house 5 toward thesemiconductor wafer W under the control of the controller 3. Morespecifically, the controller 3 controls the trigger control circuit 38to turn on the trigger switches SW in the short-pulse circuit SP and inthe long-pulse circuit LP connected to all of the flash lamps FLsimultaneously and in unison. At this time, part of the flash of lightemitted from the flash lamps FL travels directly toward the holder 7within the chamber 6, and another part of the light is once reflected bythe reflector 52 and then travels toward the interior of the chamber 6.Such emission of the flash of light achieves the flash heating of thesemiconductor wafer W. Since the flash heating is done by the emissionof a flash of light from the flash lamps FL, the surface temperature ofthe semiconductor wafer W can be raised in a short time.

In the first preferred embodiment, the flash lamps FL1 that emit lightfor a relatively short time and the flash lamps FL2 that emit light fora relatively long time are alternately arranged in a line (FIG. 7). Inother words, the flash lamps FL1 and FL2 with different pulse widths(pulse periods of the flash of light) are arranged next to one another.Thus, the flash of light emitted from the flash lamps FL1 and the flashof light emitted from the flash lamps FL2 are uniformly superimposed onone another on the whole area of the surface of the semiconductor waferW held by the holder 7 in the treatment position. Consequently, thelight intensity in the surface of the semiconductor wafer W since thestart of light emission (since when the trigger switches SW are turnedon) transitions as shown in FIG. 9. Referring to FIG. 9, the dotted lineindicates the intensity of the flash of light emitted from the flashlamps FL1 with short pulse widths; the long and short dashed linesindicate the intensity of the flash of light emitted from the flashlamps FL2 with long pulse widths; and the solid line indicates the lightintensity obtained by superimposing both the light intensities.

The flash of light emitted from the flash lamps FL1 with short pulsewidths has a high peak intensity, but its intensity diminishes in ashort time. On the contrary, the flash of light emitted from the flashlamps FL2 with long pulse widths has a lower peak intensity than thatemitted from the flash lamps FL1, but its light intensity is maintainedfor a relatively long time. As a result of superimposing those flashesof light emitted from the flash lamps FL1 and FL2 on one another, asshown in FIG. 9, a high peak intensity is obtained immediately after thestart of light emission because the emission of the flash of light fromthe flash lamps FL1 becomes dominant. After the intensity of the flashof light from the flash lamps FL1 diminishes, a certain level of lightintensity is maintained for a relatively long time because the emissionof flashes of light from the flash lamps FL2 becomes dominant.

FIG. 10 shows the transition of the surface temperature of thesemiconductor wafer W since the start of light emission. Immediatelyafter the start of light emission, the surface temperature of thesemiconductor wafer W rapidly rises to a treatment temperature T2 whichis not less than an activation temperature of ions (in the range ofapproximately 1000° C. to 1100° C.) mainly by the flash of light with ahigh peak intensity emitted from the flash lamps FL1 with short pulsewidths. The surface temperature then gradually drops after maintained atthe activation temperature or more for a relatively long time by keepingwarm effectiveness produced mainly by the flash of light with a gentlepeak emitted from the flash lamps FL2 with long pulse widths. Thisconsequently increases the temperature of even a relatively deep portionof the semiconductor wafer W below the surface to the activationtemperature or more, thereby achieving the activation of a deepjunction. On the other hand, the temperature of the surface (a shallowportion) of the semiconductor wafer W does not rise more than necessary,which thereby prevents warpage or cracking of the semiconductor wafer W.

In this way, not only a shallow junction but also a relatively deepjunction of the semiconductor wafer W can be activated. Note that,although the duration of light emission from the flash lamps FL2 isrelatively long, approximately 3.0 milliseconds, this time is quiteshort as compared with the time necessary for thermal diffusion ofimplanted impurities so that impurity diffusion does not occur even inthe surface (shallow portion) of the semiconductor wafer W.

By preheating the semiconductor wafer W by the holder 7 prior to flashheating, the emission of the flash of light from the flash lamps FL canrapidly increase the surface temperature of the semiconductor wafer W upto the treatment temperature T2.

After waiting in the treatment position for about 10 seconds after thecompletion of the flash heating, the holder 7 is moved downwardly againto the transfer position shown in FIG. 1 by the holder elevatingmechanism 4, and the semiconductor wafer W is transferred from theholder 7 to the support pins 70. Subsequently, the gate valve 185 opensthe transport opening 66 having been closed, and the semiconductor waferW placed on the support pins 70 is transported outwardly by thetransport robot outside the heat treatment apparatus 1. This completesthe flash heating process of the semiconductor wafer W in the heattreatment apparatus 1.

During the heat treatment of the semiconductor wafer W in the heattreatment apparatus 1, as discussed above, nitrogen gas is continuouslysupplied into the chamber 6. The amount of supply of nitrogen gas shallbe approximately 30 liters per minute when the holder 7 is in thetreatment position and it shall be approximately 40 liters per minutewhen the holder 7 is in any position other than the treatment position.

As so far described, in the first preferred embodiment, the flash lampsFL1 with short pulse widths and the flash lamps FL2 with long pulsewidths are alternately arranged in a line (FIG. 7). When the thirtyflash lamps FL have a constant pulse width as in the past, an attempt toincrease the temperature of even a deep portion of the semiconductorwafer W below the surface to the activation temperature or more causesthe temperature of a shallow portion to be excessively increased morethan necessary, thereby causing wafer warpage or cracking due to thermalstress as previously discussed. On the contrary, when the temperature ofa shallow portion near the surface of the semiconductor wafer W isincreased to an optimum temperature, a deep portion of the semiconductorwafer W does not reach the activation temperature, so that theactivation of a deep junction is difficult.

By alternately arranging the flash lamps FL1 with short pulse widths andthe flash lamps FL2 with long pulse widths as in the present preferredembodiment, the flash of light with a high peak intensity from the flashlamps FL1 and the flash of light with a gentle peak from the flash lampsFL2 can be uniformly superimposed on one another on the whole surface ofthe semiconductor wafer W. Thus, the temperature of even a deep portionof the semiconductor wafer W can be increased to the activationtemperature or more without heating a shallow portion near the surfaceof the semiconductor wafer W more than necessary. This achieves theactivation of a deep junction without causing warpage or cracking of thesemiconductor wafer W.

<2. Second Preferred Embodiment>

Next, a second preferred embodiment of the invention is described. Theoverall construction of a heat treatment apparatus of the secondpreferred embodiment is generally the same as that of the firstpreferred embodiment shown in FIGS. 1 and 5. The procedure for thetreatment of the semiconductor wafer W in the heat treatment apparatusof the second preferred embodiment is also the same as that described inthe first preferred embodiment. The heat treatment apparatus of thesecond preferred embodiment differs from that of the first preferredembodiment in the arrangement of the flash lamps FL.

FIG. 11 shows the arrangement of a plurality of flash lamps FL in thesecond preferred embodiment. In the second preferred embodiment, theflash lamps FL1 and the flash lamps FL2 are arranged to intersect withone another in the form of parallel crosses. Specifically, the pluralityof flash lamps FL are divided into two lamp groups each consisting of anequal number of flash lamps FL, one of the lamp groups (a first lampgroup) being connected to the short-pulse circuits SP and the other ofthe lamp groups (a second lamp group) being connected to the long-pulsecircuits LP. The flash lamps FL1 forming the first lamp group arearranged in a plane in parallel with one another in a horizontaldirection. Also, the flash lamps FL2 forming the second lamp group arearranged in a plane in parallel with one another in a horizontaldirection. Then, the plane of arrangement of the first lamp group andthe plane of arrangement of the second lamp group are superimposed oneach other so that the flash lamps FL1 and the flash lamps FL2 intersectwith one another in the form of parallel crosses. The short-pulsecircuits SP and the long-pulse circuits LP are identical to those in thefirst preferred embodiment, and the remaining part of the constructionother than the arrangement of the flash lamps FL is the same as that inthe first preferred embodiment. Note that either one of the arrangementsof the flash lamps FL1 and FL2 may be overlaid on top of the other.

Even with the crossing arrangement as in the second preferredembodiment, the flash of light emitted from the flash lamps FL1 and theflash of light emitted from the flash lamps FL2 are uniformlysuperimposed on one another on the whole surface of the semiconductorwafer W held by the holder 7 in the treatment position. Consequently,the light intensity in the surface of the semiconductor wafer W sincethe start of light emission transitions as shown in FIG. 9, and thesurface temperature of the semiconductor wafer W transitions as shown inFIG. 10. In other words, if, as in the second preferred embodiment, theflash lamps FL1 with short pulse widths and the flash lamps FL2 withlong pulse widths are arranged to intersect with one another in the formof parallel crosses, the flash of light with a high peak intensity fromthe flash lamps FL1 and the flash of light with a gentle peak from theflash lamps FL2 are uniformly superimposed on one another on the wholesurface of the semiconductor wafer W, and the temperature of even a deepportion of the semiconductor wafer W can be increased to the activationtemperature or more without heating a shallow portion near the surfaceof the semiconductor wafer W more than necessary. This achieves theactivation of a deep junction without causing warpage or cracking of thesemiconductor wafer W.

<3. Third Preferred Embodiment>

Next, a third preferred embodiment of the invention is described. Theoverall construction of a heat treatment apparatus of the thirdpreferred embodiment is generally the same as that of the firstpreferred embodiment shown in FIGS. 1 and 5, and the procedure for thetreatment of the semiconductor wafer W in the heat treatment apparatusof the third preferred embodiment is also the same as that described inthe first preferred embodiment. The heat treatment apparatus of thethird preferred embodiment differs from that of the first preferredembodiment in the shape and arrangement of the flash lamps FL.

FIG. 12 shows the arrangement of a plurality of flash lamps FL in thethird preferred embodiment. While, in the first and second preferredembodiments, the flash lamps FL are rod-like lamps each including thecylindrical glass tube 92, the flash lamps FL in the third preferredembodiment are point source lamps (e.g., spherical lamps). The pluralityof point source lamps or flash lamps FL are divided into two lamp groupseach consisting of an equal number of flash lamps FL. One of the lampgroups (a first lamp group) is connected to the short-pulse circuits SP,and the other of the lamp groups (a second lamp group) is connected tothe long-pulse circuits LP in the same manner as in the first and secondpreferred embodiment. In the third preferred embodiment, the flash lampsFL1 and the flash lamps FL2 are alternately arranged both in thelongitudinal and lateral directions. In other words, the flash lamps FL1and the flash lamps FL2 are arranged in a checkered pattern. Theshort-pulse circuits SP and the long-pulse circuits LP are the same asthose in the first preferred embodiment, and the remaining part of theconstruction other than the shape and arrangement of the flash lamps FLis the same as that in the first preferred embodiment.

Even with the lamp arrangement as in the third preferred embodiment, theflash of light emitted from the flash lamps FL1 and the flash of lightemitted from the flash lamps FL2 are uniformly superimposed on oneanother on the whole surface of the semiconductor wafer W held by theholder 7 in the treatment position. Consequently, the light intensity inthe surface of the semiconductor wafer W since the start of lightemission transitions as shown in FIG. 9, and the surface temperature ofthe semiconductor wafer W transitions as shown in FIG. 10. In otherwords, if, as in the third preferred embodiment, the flash lamps FL1with short pulse widths and the flash lamps FL2 with long pulse widthsare arranged in a checkered pattern, the flash of light with a high peakintensity from the flash lamps FL1 and the flash of light with a gentlepeak from the flash lamps FL2 are uniformly superimposed on one anotheron the whole surface of the semiconductor wafer W, and the temperatureof even a deep portion of the semiconductor wafer W can be increased tothe activation temperature or more without heating a shallow portionnear the surface of the semiconductor wafer W more than necessary. Thisachieves the activation of a deep junction without causing warpage orcracking of the semiconductor wafer W.

<4. Modifications>

Although the preferred embodiments according to the invention have beendescribed hereinabove, various modifications in addition to the abovecan be made therein without departing from the spirit and scope of theinvention. For example, while in the preferred embodiments describedabove, the start timing of light emission from the flash lamps FL1 andthe start timing of light emission from the flash lamps FL2 aresimultaneous with each other, they may differ. FIG. 13 illustrates thetransition of the light intensity in the surface of the semiconductorwafer W in the case where the start timing of light emission from theflash lamps FL1 with short pulse widths is earlier than the start timingof light emission from the flash lamps FL2 with long pulse widths. Morespecifically, the controller 3 controls the trigger control circuit 38so that, after the trigger switches SW in the short pulse circuits SPconnected to the flash lamps FL1 are turned on, then the triggerswitches SW in the long pulse circuits LP connected to the flash lampsFL2 are turned on.

On the other hand, FIG. 14 illustrates the transition of the lightintensity in the surface of the semiconductor wafer W in the case wherethe start timing of light emission from the flash lamps FL1 with shortpulse widths is later than the start timing of light emission from theflash lamps FL2. More specifically, the controller 3 controls thetrigger control circuit 38 so that, after the trigger switches SW in thelong pulse circuits LP connected to the flash lamps FL2 are turned on,then the trigger switches SW in the short pulse circuits SP connected tothe flash lamps FL1 are turned on. In FIGS. 13 and 14, as in FIG. 9, thedotted lines indicate the intensity of the flash of light from the flashlamps FL1 with short pulse widths; the long and short dashed linesindicate the intensity of the flash of light from the flash lamps FL2with long pulse widths; and the solid lines indicate the light intensityobtained by superimposing both the light intensities. The arrangement ofthe flash lamps FL may be any of those in the first to third preferredembodiments described above.

Even if the flash lamps FL1 and the flash lamps FL2 start light emissionwith different timing as shown in FIGS. 13 and 14, the flash of lightwith a high peak intensity from the flash lamps FL1 and the flash oflight with a gentle peak from the flash lamps FL2 are uniformlysuperimposed on one another, so that the temperature of even a deepportion of the semiconductor wafer W can be increased to the activationtemperature or more without heating a shallow portion near the surfaceof the semiconductor wafer W more than necessary. This achieves theactivation of a deep junction without causing warpage or cracking of thesemiconductor wafer W. Besides, it is possible, according to differencesin the start timing of light emission, to adjust as appropriate thedepth of a portion whose temperature is increased to the activationtemperature or more, and the surface temperature of the semiconductorwafer W. This produces a wide range of variations of the heat treatmentpattern.

The pattern of arrangement of the flash lamps FL are not limited tothose in FIGS. 7, 11, and 12, and various patterns can be adopted.However, an uneven distribution of the flash lamps FL1 with short pulsewidths or the flash lamps FL2 with long pulse widths (e.g., referring toFIG. 7, only the flash lamps FL1 are arranged on the right half of thespace and only the flash lamps FL2 on the left half) results in unevenactivation because an area irradiated with only a flash of light with ahigh peak intensity and an area irradiated with only a flash of lightwith a gentle peak are produced on the surface of the semiconductorwafer W. For this reason, the lamp arrangements as shown in FIGS. 7, 11,and 12 are preferable, in which the flash of light with a high peakintensity from the flash lamps FL1 and the flash of light with a gentlepeak from the flash lamps FL2 are uniformly superimposed on one another.

While, in the preferred embodiments described above, the flash lamps FL1and the flash lamps FL2 are equal in number, the invention is notlimited thereto and either of the flash lamps FL1 and FL2 may be largein number. In other words, the construction may be such that the firstlamp group consisting of part of a plurality of flash lamps is connectedto the short-pulse circuits SP, and the second lamp group consisting ofthe remainder of the flash lamps are connected to the long-pulsecircuits LP.

In each of the short-pulse circuits SP and the long-pulse circuits LP inthe preferred embodiments described above, the power supply unit 95shown in the configuration of FIG. 6 is a constant-voltage power supplyto supply a certain constant voltage to the capacitor 93, but theinvention is not limited thereto. The power supply unit 95 in each ofthe short-pulse circuits SP and the long-pulse circuits LP may be avariable-voltage power supply so that a desired voltage can be appliedto the capacitor 93 thereby to make variable a charge voltage stored inthe capacitor 93. In such a configuration, by making variable the valueof power supply voltage supplied from the power supply unit 95, theshort-pulse circuits SP and the long-pulse circuits LP can have morediscretion in setting the charge voltage to be stored in theirrespective capacitors 93. Thus, the amount of discharge in each of theshort-pulse circuits SP and the long-pulse circuits LP can be changed byany combination of the charge voltages stored in the short-pulsecircuits SP and the long-pulse circuits LP. This makes it possible tovary the intensity of light discharged from the flash lamps FL1connected to the short-pulse circuits SP and the intensity of lightdischarged from the flash lamps FL2 connected to the long-pulse circuitsLP. Combining this with the aforementioned step of varying the durationof light emission gives the apparatus according to the invention morediscretion in applying to the semiconductor wafer W the required amountof heat for the required amount of time and in thereby activating anarea at a desired depth below the surface of the semiconductor wafer Win accordance with the required process.

The flash lamps FL are not limited to xenon flash lamps but may bekrypton flash lamps.

While the hot plate 71 is used as an assist-heating element in thepreferred embodiments described above, a plurality of lamp groups (e.g.,a plurality of halogen lamps) may be provided under the holder 7 whichholds the semiconductor wafer W to emit light therefrom, therebyachieving assist-heating.

In the preferred embodiments described above, the ion activation processis performed by irradiating the semiconductor wafer with light, but theinvention is not limited to thereto. For example, the heat treatmentapparatus according to the invention may be used in the construction offorming a cobalt silicide layer or a nickel silicide layer, therebyforming a silicide layer with sufficient film thickness. Further, asubstrate to be treated by the heat treatment apparatus according to theinvention is not limited to a semiconductor wafer. For example, the heattreatment apparatus according to the invention may perform heattreatment on a glass substrate formed with various silicon filmsincluding a silicon nitride film, a polycrystalline silicon film, andthe like. As an example, silicon ions are implanted into apolycrystalline silicon film formed on a glass substrate by a CVDprocess to form an amorphous silicon film, and a silicon oxide filmserving as an anti-reflection film is formed on the amorphous siliconfilm. In this state, the heat treatment apparatus according to theinvention may irradiate the entire surface of the amorphous silicon filmwith light to polycrystallize the amorphous silicon film, therebyforming a polycrystalline silicon film.

As another alternative, the heat treatment apparatus according to theinvention can perform light irradiation on a TFT substrate constructedin such a way that an underlying silicon oxide film and a polysiliconfilm that is produced by crystallization of amorphous silicon are formedon a glass substrate and the polysilicon film is doped with impuritiessuch as phosphorus or boron, thereby activating the impurities implantedin the doping step.

While the invention has been described in detail, the foregoingdescription is in all aspects illustrative and not restrictive. It isunderstood that numerous other modifications and variations can bedevised without departing from the scope of the invention.

What is claimed is:
 1. A method for irradiating a substrate with flashesof light to heat the substrate, the method comprising: (a) a firstirradiation step of irradiating the substrate with a flash of light froma first flash lamp, to increase a surface temperature of the substrateto a predetermined temperature or more, the flash of light having afirst peak intensity; and (b) a second irradiation step of irradiatingthe substrate with a flash of light from a second flash lamp, tomaintain the surface temperature of the substrate at the predeterminedtemperature or more, the flash of light having a second peak intensitylower than the first peak intensity.
 2. The method according to claim 1,wherein the flash of light having the first peak intensity has a pulsewidth shorter than a pulse width of the flash of light having the secondpeak intensity.
 3. The method according to claim 1, wherein thesubstrate is heated to produce a metal silicide.